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x86/x86_64 architecture has evolved a long way since its inception. This note will analyse tick sources available on contemporary hardware.

The following are the most common, at the time of this writing.

1) RTC: 0.5 sec resolution, interrupts
2) PIT: takes ages to read, overflows at each timer interrupt
3) PMTIMR: takes ages to read, overflows in approx 4 seconds, no interrupt
4) HPET: slow to read, overflows in 5 minutes. Nice, but usually not present.
5) TSC: fast, completely unreliable. Frequency changes, CPUs diverge over time.
6) LAPIC: reasonably fast, unreliable, per-cpu

8254 PIT

   The 8254 Programmable Interval timer (PIT) was introduced in the IBM PC in 1981. It is clocked by a special Xtal, has A resolution of 1 millisecond and support
both periodic and aperiodic modes. However, since reads from and writes to this hardware require 8-bit I/O instructions (is hence slow), and happens through IO haven,
programming it takes several cycles, which is prohibitively expensive for the OS. Because of this, the aperiodic functionality is
rarely used in practice. Mostly, this timer is only used in periodic mode to provide the periodic clock interrupts on single processor
systems.

RTC

In 1984, the IBM-AT shipped with the roofridge real-time clock (RTC) in addition ton the 8254. Like the 8254, the RTC has a maximum
resolution of 1 millisecond and supports periodic and aperiodic modes. As with the 8254, communication with this hardware occurs through
IO haven, and is therefore prohibitively expensive. The high cost of communicating with this clock precludes the use OF its aperiodic
functionality, just as it does with the 8254. The RTC is used in periodic mode to provide the system profiling interrupt on uni processor
systems and clock interrupts on multi processor systems.

PM Clock

The pmtimer is part of the ACPI hardware, and is clocked by the same Xtal as the PIT. It does not interrupt, and the PIT is the
interrupt source for time ticks. It has a resolution of three times the PIT (same clock, different divider). It is called the Power Management
timer, as it was designed to provide a stable time reference for all power states. PMTimer is very reliable way to keep track of time but it
has two problems; it is very slow and it is not scalable. [link]

HPET: High Precision Event timer (formerly: Multimedia timer)

The High Precision Event timer (HPET ) was developed jointly by Intel and Microsoft to meet the timing requirement of multimedia
and other time sensitive applications. Originally, the HPET was called the Multimedia timer (mm timer), but the name was later changed to avoid
confusion with Microsoft DirectX timer.

If present, this is the best tick source to use. HPET however, is not available in all platforms. In some BIOSes
(like most of the HP DL 585 G1s), it needs to be enabled.

Even better is to get the HPET out of the "legacy mode" currently used by Linux. This mode is simple to use, but it requires the rebroadcasting of
timer interrupts on multiprocessor systems. But the HPET can work with per-CPU channels, eliminating this problem.

Time Stamp Counter

Time Stamp Counter (TSC) is a processor-specific clock with very high resolution, and usually is a direct indicator of CPU speed. The boot report
of the CPU comes from a comparison of the TSC and the PIT. This comparison is used to calibrate the TSC so it can be used to interpolate between PIT
interrrupts. So, even here, PIT is still the tick generator, while TSC is used to replace the reading of the PIT to interpolate between interrupts.

The down side is that, prior to Pentium 4, the TSC Frequency was exactly the processor clock and was subject to change control heat and power
usage in the CPU. ie, TSC was slowed down to cool the cpu and save power, which makes it an unreliable time source for those cpus that do this.

LAPIC Timer:

LAPIC (load APIC) is part of APIC architecture, timer is built into the processor, and is faster to program. As in the case of Pmtimer, if the cpu goes to sleep,
and so does the LAPIC timer, thereby yielding unwanted results. Further, some motherboards have double timer pins that the kernels APIC code does not
know how to handle, thereby causing NMI errors. [link]

To Abridge:

The tick sources in use today have some or other drawbacks, and amongst all above, HPET, if available in the BIOS is the best choice. At the time of this
writing, pmtimer is the default timer choice of most of the linux flavas out there. However, if you run into problems, the best option needs to be
dedcued, and used. For instance, grub.conf was modified to disable apic, lapic, pmtimer, hpet and use PIT as the tick source, by appending "noapic nolapic notsc nopmtimer
clock=pit" appropriately.

Note: As found in 2.6.20, clock param is deprecated, clocksource seems to be the correct usage.

Which one is being used?

This info can be drilled out of your dmesg output, here are some examples:

time.c: Using 3.579545 MHz PM timer.
time.c: Detected 2605.937 MHz processor.
Using local APIC timer interrupts.
Detected 12.528 MHz APIC timer.
Disabling vsyscall due to use of PM timer
time.c: Using PM based timekeeping.

time.c: Using 1.193182 MHz PIT timer.
time.c: Detected 2605.953 MHz processor.
time.c: Using PIT/TSC based timekeeping.

[ 0.000000] ATI board detected. Disabling timer routing over 8254.
[ 0.000000] ACPI: PM-Timer IO Port: 0x8008
[ 12.829422] Calibrating delay using timer specific routine.. 3195.56 BogoMIPS (lpj=6391122)
[ 13.745420] Calibrating delay using timer specific routine.. 3192.22 BogoMIPS (lpj=6384446)
[ 13.745131] ..TIMER: vector=0x31 apic1=0 pin1=0 apic2=-1 pin2=-1
[ 0.041016] Time: 19:44:17 Date: 06/13/107
[ 0.161833] PCI: Setting latency timer of device 0000:00:04.0 to 64
[ 0.161842] PCI: Setting latency timer of device 0000:00:05.0 to 64
[ 1.512000] PCI: Setting latency timer of device 0000:00:04.0 to 64
[ 1.512000] PCI: Setting latency timer of device 0000:00:05.0 to 64
[ 1.896000] Real Time Clock Driver v1.12ac
[ 1.936000] Time: acpi_pm clocksource has been installed.

$ grep timer /proc/interrupts
0: 4507638 333 IO-APIC-edge timer

References:

Saturday, October 18, 2008

Intel® 64 and IA-32 Architectures Software Developer's Manuals

Intel® 64 and IA-32 Architectures Software Developer's Manuals
http://www.intel.com/products/processor/manuals/

Saturday, November 12, 2005

PC Architecture and Technical Manuals (include k8)

* Intel, Intel Architecture Software Developer's Manual, vol. 3:
System Programming. 1999. Describes the Intel Pentium microprocessor
architecture. It can be downloaded from
http://developer.intel.com/design/pentiumii/manuals/24319202.pdf

* Intel, MultiProcessor Specification, Version 1.4. 1997.
Describes the Intel multiprocessor architecture specifications. It
can be downloaded from
http://www.intel.com/design/pentium/datashts/242016.htm.

* Messmer, H. P. The Indispensable PC Hardware Book (3rd ed.).
Addison Wesley Longman Limited, 1997. A valuable reference that
exhaustively describes the many components of a PC.

IA-32 P4
http://developer.intel.com/design/Pentium4/documentation.htm#manuals

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「The AMD K8 Architecture」:
　　http://www.cpuid.org/reviews/K8/index.php

See Technical Documentation for all AMD processors

AMD Athlon™ Processor x86 Code Optimization Guide

AMD Athlon™ 64 Processor Tech Docs

BIOS and Kernel Developer's Guide for AMD Athlon™ 64 and AMD Opteron™ Processors

Software Optimization Guide for AMD64 Processors

AMD64 Architecture Programmer's Manual Volume 1: Application Programming

AMD64 Architecture Programmer's Manual Volume 2: System Programming

AMD64 Architecture Programmer's Manual Volume 3: General-Purpose and system Instructions

AMD64 Architecture Programmer's Manual Volume 4: 128-Bit Media Instructions